Getting Started Guide
copy; 2015, Imagination Technologies
Version 1.1, 22 July 2015
Table of Contents
Section 2 . A Brief History of the MIPS Architecture 1
Section 3 . The MIPSfpga Core and System 2
Section 4 . How to use MIPSfpga 7
Section 4.2 . Hardware: Running MIPSfpga on an FPGA 13
Section 4.2.1 . Nexys4 DDR FPGA Board 14
Section 4.2.2 . DE2-115 FPGA Board 17
Section 5 . MIPSfpga Interfaces 22
Section 5.1 . MIPSfpga Interface Signals 23
Section 5.2 . AHB-Lite Interface 24
Section 5.3 . FPGA Board Interfaces 25
Section 5.4 . EJTAG Interface 26
Section 6 . Example Programs 27
Section 6.1 . Example: Memory-Mapped Outputs (LEDs) 27
Section 6.2 . Example: Memory-Mapped I/O (Switches and LEDs) 28
Section 6.3 . Simulation: Running an Example Program in Simulation 30
Section 6.4 . Hardware: Running an Example Program in Hardware 31
Section 6.4.1 . Nexys4 DDR FPGA Board 32
Section 6.4.2 . DE2-115 FPGA Board 37
Section 7 . Programming using Codescape 40
Section 7.1 . MIPSfpga Boot Code 41
Section 7.2 . Compiling C and Assembly Code using Codescape 42
Section 7.2.1 . Example C Program 42
Section 7.2.2 . Example MIPS Assembly Program 44
Section 7.3 . Simulation of a Compiled Program 45
Section 7.4 . Hardware: Resynthesizing MIPSfpga with a Compiled Program 52
Section 7.5 . Downloading a Compiled Program using EJTAG 52
Section 7.6 . Debugging Compiled Programs on MIPSfpga using Codescapes gdb 56
Section 8 . Summary and a Look Ahead 60
Section 10 . Acknowledgements 63
Appendix A. Installing ModelSim PE Student Edition 65
Appendix B. Installing Vivado for the Nexys4 DDR FPGA Board 71
Appendix C. Installing Quartus II for the DE2-115 FPGA Board 84
Appendix D. Installing Programming Tools 95
Appendix E. Setting up a Project in ModelSim 99
Appendix F. Using Vivados Built-In Simulator (XSim) 111
Appendix G. Reducing Compile Time in Quartus II 116
Appendix H. Reducing Compile Time in Vivado 122
Appendix I. Porting MIPSfpga to Other FPGA Boards 125
Appendix J. Bus Blaster Interface 128
MIPSfpga License Agreement 132
MIPSfpga Getting Started Guide
. Introduction
MIPSfpga is an Imagination MIPS32reg; microAptiv microprocessor with cache and memory management unit for educational use. It comes with complete Verilog code suitable for simulation and for implementation on a field-programmable gate array (FPGA) board.
MIPS processors have been used in commercial products and studied by computer architecture students for decades. This Getting Started Guide introduces the first freely available commercial MIPS core. The guide describes how to use the MIPS core in simulation and in hardware on an FPGA.
This guide begins with an overview of the MIPS core, called MIPSfpga, followed with detailed steps on how to simulate and run MIPSfpga on an FPGA. We also describe the MIPSfpga cores interface signals and how to write and run programs on the MIPSfpga core. The guide concludes with an overview of additional references that will aid in understanding the MIPSfpga core specifically and the MIPS architecture generally.
The use of this industrial-strength MIPS core is an excellent complement to many courses, including courses in computer architecture, embedded systems, and system-on-chip design. Section 8 lists recommended textbooks that describe the MIPS architecture in detail. This guide assumes that you are familiar with MIPS assembly and machine language and basic pipelined processor architecture as described in such books.
All of the documents referred to in this guide are found in the MIPSfpga folder provided by Imagination Technologies with this Getting Started Guide.
. A Brief History of the MIPS Architecture
MIPS is one of the original Reduced Instruction Set Computer (RISC) architectures. Growing out of research at Stanford University in 1981 to revolutionize the efficiency of computer architectures, it was commercialized in 1984 by MIPS Computer Systems and acquired by Imagination Technologies in 2013.
MIPS processors became the brains of the high-performance Silicon G
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